Half-Bridge Power Stages
Control a switching node with high-side and low-side devices while preventing shoot-through.
A half-bridge is a two-way railway switch: one device connects the midpoint upward to the DC bus and the other connects it downward to ground, but both tracks must never be selected together.
A half-bridge places two power switches in series across a DC bus. Their midpoint is the switch node. Turning on the high-side device connects the node near the positive bus; turning on the low-side device connects it near the negative rail. Filters, transformers or motor windings convert those pulses into useful voltage and current.
The commands must be complementary with a deliberate interval when both devices are off. This dead time accounts for propagation delay and finite switching time. If both devices conduct together, shoot-through creates a low-impedance path across the DC bus and can destroy the switches.
During dead time an inductive load current cannot stop instantly. It commutates through a body diode or another freewheel path, which changes voltage stress and loss. Excess dead time can therefore increase diode conduction and distort the output even though too little dead time is dangerous.
Real design requires voltage and current margin, gate-driver undervoltage lockout, local decoupling, short commutation loops, thermal analysis and careful probing. Parasitic inductance turns fast di/dt into overshoot according to V = L di/dt.
Control a switching node with high-side and low-side devices while preventing shoot-through.
Core ideas
- The midpoint switches between the DC rails.
- Dead time prevents same-leg shoot-through.
- Inductive current chooses a freewheel path during commutation.
Duty ratio: D = ton/TsOvershoot contribution: V = L × di/dtApproximate conduction loss: P ≈ Irms²RDS(on)Work through a practical example
1A 48 V half-bridge switches at 100 kHz, so one period is 10 μs.
2A 40% high-side command gives an ideal on-time of 4 μs before accounting for dead time.
3With 200 ns dead time at each transition, the effective pulse and diode-conduction intervals differ from the ideal command.
4Verify both gate waveforms and the switch node with suitable differential measurement before connecting a high-power load.
Driving the high-side and low-side MOSFETs from identical overlapping PWM signals, or inserting dead time without checking its effect on loss and distortion.