Flip-flops, Registers and Clock Timing
Understand stored bits, clock edges, setup and hold time, and asynchronous inputs.
A flip-flop is a camera that captures one bit at a clock edge. The input must hold still around the instant of the photograph.
A D flip-flop stores one bit. At its active clock edge it captures D, then Q reflects that captured value after a clock-to-Q delay. Between edges, Q retains the stored state rather than following D continuously. A register is a group of flip-flops used to store a multi-bit word.
Setup time requires the input to be stable before the capturing edge; hold time requires stability afterward. If either requirement is violated, the device can enter metastability and take an unpredictable time to settle. A digital simulation using only zero and one does not automatically represent this analog behavior.
In a synchronous path, one register launches data, combinational logic processes it, and another register captures it on a later edge. The clock period must accommodate clock-to-Q delay, logic delay, setup time and a timing budget for clock uncertainty. Hold requirements are a separate minimum-delay check and are not fixed merely by reducing clock frequency.
A button or signal from another clock domain is asynchronous to the receiving clock. A properly designed synchronizer reduces the probability that metastability propagates, but cannot make it mathematically zero. A two-stage synchronizer can be appropriate for a single-bit level. Multi-bit data or short pulses require additional protocols such as handshakes or asynchronous FIFOs.
Understand stored bits, clock edges, setup and hold time, and asynchronous inputs.
Core ideas
- Registers store state between clock edges.
- Setup and hold constraints protect reliable capture.
- Do not synchronize a multi-bit bus by treating each bit as unrelated.
Tclock ≥ tCQ + tlogic + tsetup + timing marginfclock = 1 / TclockWork through a practical example
1Assume tCQ = 1 ns, logic delay = 6 ns and setup = 1 ns.
2Before additional uncertainty, the minimum clock period is 8 ns.
3This corresponds to an upper bound of 125 MHz for this simplified setup calculation.
4Add the actual clock uncertainty and check hold timing and all other paths before selecting a clock.
Thinking a two-flip-flop synchronizer guarantees zero failures or safely transfers every multi-bit value.