Finite State Machines for Digital and Embedded Design
Organize control behavior into explicit states, transitions and outputs.
An FSM is a small rulebook: what you do next depends on both the event and the page you are currently on.
A finite state machine represents behavior using a finite set of states. Inputs and the current state determine the next state. This is useful when the same input must mean different things at different times. A start button may begin a measurement in Idle but be ignored while already Measuring.
Define the states before writing nested if statements. For a sample collector, use Idle, Collecting and Ready. In Idle, wait for a debounced start event. In Collecting, accept samples until the target count is reached. In Ready, expose the result and wait for acknowledgment. Decide how reset and unexpected events behave in every state.
A Moore-style output depends on the state; a Mealy-style output can also depend directly on the current inputs. In either case, specify when outputs change. Firmware should perform entry actions once rather than accidentally repeating them on every loop iteration. Digital hardware needs a clear clocked state register and combinational next-state logic.
Keep event production separate from state transitions. The button module should deliver one press event, not an unfiltered voltage level. A timer can supply a timeout event without blocking execution. This separation lets you test the control logic using a written sequence of events before connecting real hardware.
Organize control behavior into explicit states, transitions and outputs.
Core ideas
- State carries the relevant history of the system.
- Specify reset and unexpected inputs.
- Keep event detection separate from the transition rules.
next_state = transition(current_state, event)Moore output = function(current_state)Work through a practical example
1Reset enters Idle and clears the sample count.
2A start event moves to Collecting.
3The 100th accepted sample moves to Ready and freezes the result.
4An acknowledge event returns to Idle. A start event in Ready is ignored by this chosen design.
Changing state in several unrelated places or using blocking delays to represent a waiting state.